Coming from an ASIC background, I generally don’t use the FPGA tool IDEs. Sure they have a place for debug, but for consistency especially when using source control systems, scripting is the way forward. Both Intel and Xilinx have good support for TCL in their tool chains, but I find this a bit cumbersome.

I’ve built a set of python scripts called rmake, which can be used to both simulate and drive the FPGA vendor tools with minimum pain. It also makes it really quick to play around or add new cores.

If we look at Loader, a simple reference design which uses the Replay framework. This core shows how to provide an OSD (on screen display) over a video background picture stored in DRAM. It can also play audio samples from the sd-card, a path which is more commonly used for hard / floppy disk emulation.

These are all the source files in the core/rtl directory:

_src.txt contains  :

loader_video.vhd
loader_top.vhd
core_pack.vhd
core_top.vhd

and _deps.txt:

[R1] replay_common/replay_targets/R1
[V4] replay_common/replay_targets/V4

The support files which are common to all cores are in the replay_common repository. The [R1] and [V4] allow changes based on the build target.

From the core directory I can do :

rmake sim  which will create a local work directory and compile all the files for Intel Modelsim

rmake ise –target=R1  will call the Replay1 XIlinx ISE flow and produce an FPGA file

rmake qrt –target=V4 does the same for Intel Quartus for the Vidor 4000

and we can also rmake viv for Xilinx Vivado, targeting the Zynq Ultrascale currently.

Cool eh?

Having the same build system for simulation makes it really easy to test the cores. The build system has /tb directories for each target which include a model of the board including DDR (Replay1) or SDR (Vidor) memory and can capture and store the video output to a file. Here is the result of simulating one frame of the Loader core :

The very talented Arnim Laeuger has been working with our new Replay framework to bring his games to the Arudino Vidor 4000 FPGA platform (called V4 from here down)

The Vidor is a low cost FPGA board available here : https://store.arduino.cc/mkr-vidor-4000

To support the cores, the firmware which runs on the Replay1 board ARM can now be built for the SAMD21 within the Arduino IDE.

We have abstracted the FPGA framework and created a build system so that the same core can be built for the V4 and the Replay1 board, as well as the up-coming Replay2 board.

Here we have the Videopac core with KC Munchkin on V4

And here Colecovision Frogger on the V4, with Frogger on Replay1’s Videopac core in the small picture.

Ignore the configured time here, we had a bug….

We’ve started to put some binary releases here on github here, https://github.com/fpgaarcade

Our aim is to include every FPGA game we can find (including lots of my own stuff which never made it onto Replay1) into this new framework and publish it asap.

I have an original Replay1a board back for repair at the moment, so I thought I would take a picture of the family together.

R1a on the left. R1b next with the 68060 daughter board.

Top right the Arduino MKRVidor4000 we are targeting to be a low cost R1 replacement.

Bottom right the Zynq Ultrascale board which we are using to evaluating the SOC for R2. I’m currently designing a small expansion board which will let me test analogue and digital video out from the FPGA fabric.

Exciting times!

/Mike

We’ve sold all the boards in Europe. Jim Drew still has one or two in the US which can be shipped anywhere.

If you have a Replay1 board, this is your last change to get one! Ping me or Jim.

Cheers,

Mike