Well, actually the last (I thought) Replay1 shipped years ago, but I’ve had one sitting around which failed production test. When a core boots up, the ini file for that core tells the software which files to upload into the FPGA, and optionally these can be read back to verify everything is working correctly.

The system uses the same mechanism at start-up to check the DDR memory is behaving itself. This particular board was unique in failing this test.

2.827: [config.c:2095] tDirScan allocated: 7936 bytes
2.929: [fpga.c:363] FPGA:DRAM enabled, running test.
WARN: !!Match fail Addr: 0
2.932: [messaging.c:270] DumpBuffer: address = 0020ea78 ; size = 128 (0x80) bytes
2.940: [messaging.c:316] 0x00000000: 0004FFFF FFFF0004 FFFF0004 0004FFFF

3.000: [fpga.c:393] Should be:
3.009: [messaging.c:270] DumpBuffer: address = 0012d2c4 ; size = 128 (0x80) bytes
3.011: [messaging.c:316] 0x00000000: 0000FFFF FFFF0000 FFFF0000 0000FFFF

I had already replaced the DRAM chip and it hadn’t fixed the problem. An old tip is to press down hard on the BGA – and suddenly it was all good. With little to lose (apart from maybe setting fire to my office) I gave it a good roasting with the hot air gun. 300C for a few minutes seems to have done the trick.

It’s been on soak test all day and seems ok, so now I’ve cleared my desk it’s time to bring Replay2 into the world.

/MikeJ

Here at FPGAArcade we’ve always tried to reproduce retro hardware for preservation as accurately as possible. When I did the first Pacman design years ago it was quite easy as there were only a few custom ICs. I built some analysis hardware you can find way back in the news here to compare the ASIC with my CPLD clone on the board in real time.

We have an extensive library of accurate replacements for the custom ICs on many boards. I produce CPLD modules which can be used to fix real arcade games – they are that accurate. This library is migrating to public github along with the rest of my designs asap.

I was lucky enough to be able to borrow a Gyruss game a few months ago and test the code. I decided to manufacture a 40 pin CPLD module to repair the board as well – although I’ve been waiting for it to clear customs here in Sweden for 3 weeks now 🙁

In the picture below, I’m using a Replay1 board with it’s debug daughterboard. This proves 5V isolation. Inside the FPGA I’m running the replacement design and a logic analyser core which compares all the IO in real time against the target board. Once the design is well understood, I can replace the custom ASIC with my CPLD board running the same code and see if it still works. Then we can produce an FPGA version of the complete game.

We’ve bought a number of Ultra96 boards which contain a similar FPGA to the target device on Replay2. This will kick start development, especially on the Linux side. I’m also designing a small add-on board with the video output devices we’ll use on the real board. This will allow us to run up some cores and make sure we are happy with the architecture, as well as letting me crack on with testing the new 68K core in the Amiga.